// ****************************************************************************** 
// Copyright     :  Copyright (C) 2021, Hisilicon Technologies Co. Ltd.
// File name     :  stars_vpc_s_reg_reg_offset.h
// Project line  :  Platform And Key Technologies Development
// Department    :  CAD Development Department
// Author        :  xxx
// Version       :  1
// Date          :  2020/04/01
// Description   :  The description of xxx project
// Others        :  Generated automatically by nManager V4.2 
// History       :  xxx 2021/10/23 09:27:09 Create file
// ******************************************************************************

#ifndef __STARS_VPC_S_REG_REG_OFFSET_H__
#define __STARS_VPC_S_REG_REG_OFFSET_H__

/* STARS_VPC_S_REG Base address of Module's Register */
#define SOC_STARS_VPC_S_REG_BASE                       (0x6c00000)

/******************************************************************************/
/*                      SOC STARS_VPC_S_REG Registers' Definitions                            */
/******************************************************************************/

#define SOC_STARS_VPC_S_REG_STARS_POOL_SEC_REG                (SOC_STARS_VPC_S_REG_BASE + 0x0)   
#define SOC_STARS_VPC_S_REG_STARS_DVPP_DESC_CONFIG_REG        (SOC_STARS_VPC_S_REG_BASE + 0x120) 
#define SOC_STARS_VPC_S_REG_STARS_NS_DVPP_DESC_SETTING0_REG   (SOC_STARS_VPC_S_REG_BASE + 0x130) 
#define SOC_STARS_VPC_S_REG_STARS_S_DVPP_DESC_SETTING0_REG    (SOC_STARS_VPC_S_REG_BASE + 0x140) 
#define SOC_STARS_VPC_S_REG_STARS_VPC_AXCACHE_SETTING_REG     (SOC_STARS_VPC_S_REG_BASE + 0x800) 
#define SOC_STARS_VPC_S_REG_STARS_VPC_S_AXPROT_SETTING_REG    (SOC_STARS_VPC_S_REG_BASE + 0x804) 
#define SOC_STARS_VPC_S_REG_STARS_VPC_NS_AXPROT_SETTING_REG   (SOC_STARS_VPC_S_REG_BASE + 0x808) 
#define SOC_STARS_VPC_S_REG_STARS_VPC_POOL_ENABLE_CTRL_S_REG  (SOC_STARS_VPC_S_REG_BASE + 0x840) 
#define SOC_STARS_VPC_S_REG_STARS_VPC_POOL_DISABLE_CTRL_S_REG (SOC_STARS_VPC_S_REG_BASE + 0x880) 
#define SOC_STARS_VPC_S_REG_STARS_VPC_POOL_STATUS0_S_REG      (SOC_STARS_VPC_S_REG_BASE + 0x8C0) 

#endif // __STARS_VPC_S_REG_REG_OFFSET_H__
